The 8259A PIC Handler for Hardware Interrupts under MS-DOS and Intel Architecture

 

            Computers are a combination of many pieces of hardware that have to work all together in order to process data.  Unfortunately, hardware limitation and other factors such as temperature and software can generate problems while processing the data.  These interrupts and exceptions are handled by hardware and software. 

 

            Each device that forms a computer such as the memory, video card, hard drive, and many more, notify the processor about their current state. An interrupt controller is needed when a hardware device needs immediate attention.  The interrupt controller sends a signal to the processor and the processor stops any current action and orders the interrupt handler to take action and correct the problem. When the processor executes the interrupt instruction it retrieves the interrupt code from the opcode.  Once the code is retrieved then the instruction is used to find the address of the interrupt handler and correct the problem, then the processor returns to its previous state.  Hardware interrupts are asynchronous to the program that it's been executed since not the same errors happen at the same point of the program.

            .

            There are two basic type of hardware interrupt: Non-Maskable Interrupts (NMI), which is the result of serious hardware problem, and (Maskable) Interrupt Requests (IRQ).  The Interrupt Driven I/O and the Polling section I/O devices can be serviced in two different ways: The CPU polling method and the interrupt based technique. There is a Programmable Interrupt Controller (PIC -in MS-DOS the PIC is the 8259A) designed to permit prioritizing and handling of hardware interrupt requests from peripheral devices, mainly in a PC environment.

 

            The processor generates also a special type of interrupts named exceptions.  These exceptions are software interrupts that are generated when an unexpected event occurs.  The interrupt vector table (IVT) contains an interrupt vector for each of the 256 possible interrupts. The exception handler takes over to fix the problem and then the processor returns to its previous state.  The processor generates three types of exceptions:  Faults, Traps, and Aborts. Faults and Traps are similar because they push the address of the next instruction to the stack and waits for the exception handler to fix the problem.   Aborts occur when sever errors arise and they are not recoverable.

 

            The steps that the processor takes when it finds and interrupt are:

            1.  Push Flags, CS (Code Segment) and IP (Instruction Pointer) registers to the stack in this order.

2.  Multiply interrupt number by 4 and use the resulting number as an offset into the interrupt table.

            3.  Get far address (CS and IP) of the interrupt handler from the table entry.

            4.  Disable interrupts.

            5.  Jump to execute the handler.

6.  When the handler code ends (an IRET instruction is executed), pop CS, IP and the flags from the stack so that control returns to the currently active application.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The 8259A PIC Handler for Hardware Interrupts under MS-DOS

 

 

            The 8259A PIC (Programmable Interrupt Controller) is the chip that allows the existence of interrupts in the hardware.  We have to take in count the action taken by the interrupt controller from the instant the interrupt leaves the hardware device until it reaches the processor.  When a hardware interrupt is detected the interrupt controller sends the interrupt code to the processor.  The processor uses this code to index the IVT (Interrupt Vector Table) and finds the address of the interrupt handler.  The 8259A PIC acts like a bridge between the processor and the interrupt-requesting components.   The interrupt requests are transmitted first to the 8259A that in turn drives the interrupt line to the processor.   The 8259A receives the interrupt request from the I/O device and notifies the processor, the processor finishes its current program and executes a new action -an ISR (Interrupt Service Request).  Once the device is serviced then the processor finishes what it was doing when the interrupt request occurred -the PIC acts as manager hardware interrupts. 

            Eight lines are connected to the IRR (Interrupt Request Registry) in the 8259A PIC -the IRR is eight bits wide where each bit corresponds to one of the lines from ISR0 to ISR7.  If a device needs service, the device sends a high level signal to the PIC where it sets the corresponding bit in the IRR.   At the same time the PIC activates its INT line to inform the processor about the request, this starts an INTA (Interrupt Acknowledge).  Once the interrupt receives the signal it finishes the current executing instruction and outputs a first interrupt acknowledge if the interrupts is not maskable at the processor.  Once the PIC receives this INTA the highest priority is cleared in the IRR, and the corresponding bit ISR (in-service request) is set and there is not PIC activity in the data bus in this cycle.   The Processor sends a second INTA to the PIC that returns an eight-bit number onto the data bus.  This number is the interrupt handler to call, which is fetched and executed.  At the second INTA the AEOI (Automatic end of Interrupt) is set, and if not the Processor must issue an EOI to clear the ISR bit manually.

 

 

            If another interrupt it’s been received while another one it’s been processed and the EOI has not been issued yet, then the PIC will wait for this other interrupt if it’s of a lower priority.  If the new interrupt is of higher priority then the PIC will service it before it finishes the one that is currently servicing.

 

 

Class of interrupts and exceptions

 

 

Priority

Faults except debug faults

Highest

Trap instructions INTO, INT n, INT 3

 

Debug traps for this instruction

 

Debug faults for next instruction

 

NMI interrupt   

 

INTR interrupt

Lowest

 

Table 101 Priorities of Simultaneous Interrupts and Exceptions

 

            The Interrupt Controller provides 15 interrupts input, the devices connected to each input. Table 102 lists the interrupt sources on the PC.

 

Input on 8259A

Priority

80x86 INT

Device

IRQ 0

Highest

08h

Timer Chip

IRQ 1

 

09h

Keyboard

IRQ 2

 

0Ah

Cascade for controller 2 (IRQ 8-15)

IRQ 9/1

 

71h

CGA vertical retrace (and other IRQ 2 devices)

IRQ 8/0

 

70h

Real-time clock

IRQ 10/2

 

72h

Reserved

IRQ 11/3

 

73h

Reserved

IRQ 12/4

 

74h

Reserved in AT, auxiliary device on PS/2 systems

IRQ 13/5

 

75h

FPU interrupt

IRQ 14/6

 

76h

Hard disk controller

IRQ 15/7

 

77h

Reserved

IRQ 3

 

0Bh

Serial Port 2

IRQ 4

 

0Ch

Serial Port 1

IRQ 5

 

0Dh

Parallel port 2 in AT, reserved in PS/2 systems

IRQ 6

 

0Eh

Diskette drive

IRQ 7

Lowest

0Fh

Parallel Port 1

 

Table 102 Inputs of the Programmable 8259A PIC

 

            Next we will discuss the parts and in more detail the components that operate in conjunction with the CPU and the Interrupt Handler (Refer to Figure 103, pg 6).  The INT (Interrupt) output (from the peripherals devices) goes directly to the CPU interrupt input.        Two registers in cascade, the Interrupt Request Register (IRR) and the In-Service (ISR), handle the interrupts at the IR input lines. The IRR is used to store all the interrupt levels that are requesting service; and the ISR is used to store all the interrupt levels that are being serviced.  The Priority Resolver determines the priorities of the bits set in the IRR. The highest priority is selected and strobe into the corresponding bit of the ISR during INTA (Interrupt Acknowledge) pulse. The IMR (Interrupt Mask Registry) stores the bits that mask the interrupt lines to be masked. The IMR operates on the IRR (Interrupt Request Registry). Masking of a higher priority input will not affect the interrupt request lines of lower quality. INTA (Interrupt Acknowledge) pulses will cause the 8259A to release vectoring information onto the Data Bus.  Data Bus Buffer, this 3-state bi-directional 8-bit buffer is used to interface the 8259A to the system Data Bus. Control words and status information are transferred through the Data Bus Buffer.  The function of the Read/Write Control Logic is to accept Output commands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 8259A to be transferred onto the Data Bus. The CS (Chip Select) enables the 8259A. No reading or writing of the chip will occur unless the devise is selected. The WR (Write) input enables the CPU to write control words (ICW and OCW) to the 8259A. The RD (Read) input enables the 8259A to send the status of the Interrupt Request Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data Bus.  The A0 input signal is used in conjunction with WR and RD signals to write commands into the various command registers, as well as reading the various statuses register of the chip. This line can be tied directly to one of the address lines.

 

 

 

 

 

                                                                         INTA                                         INT

 

                 Data

  D7-D0                  Bus                                                                Control Logic

               Buffer

                 

               

 

 


   RD                                                                                                                                                              IR0

  WR                Read/Write                                  In                                                              Interrupt

   A0                    Logic                         Service                         Priority                     Request

                                                              Reg                            Resolver                      Reg

CS                                                        (ISR)                                                               (IRR)

 


                                                                                                                                                          IR7

 CAS 0                          Cascade

 CAS 1                         Buffer/

 CAS 2                        Comparator

                                                                                       Interrupt Mask Reg (IMR)

SP/EN

 

 


Internal Bus

 

 

Figure 103 8259A PIC Block Diagram

 

            How the instructions are arranged?  Depending in the CPU architecture the instructions to the exception handler will vary. For example, in the Pentium processor family we can find one-byte or two-byte opcode instructions (these instructions may be other than an instructions to handle an INT, as in this example).  As an example, only two of the opcode map for 1-byte opcodes is shown in Table 104.

 

 

 

0

1

2

3

4

5

6

7

0

ADD

 

 

 

 

 

PUSH

POP

 

Eb, Gb

Ev, Gv

Gv, Ev

Gv,  Ev

Al, lb

eAX, lv

ES

ES

1

ADC

 

 

 

 

 

PUSH

POP

 

Ab, Gb

Ev, Gv

Gb, Eb

Gv, Ev

Al, lb

eAX, lv

SS

SS

 

Table 104 Example of two of One-Byte Opcode Map (0-7) in Intel Arquitecture

 

 

For 1-byte opcodes, the instruction and its operands can be determined from the hexadecimal opcode. If we had the opcode 030500000000H for an ADD instruction can be interpreted from the 1-byte opcode map (See Table 104) as follows. The first digit (0) of the opcode indicates the row and the second digit (3) indicates the column in the opcode map table, which points to ADD instruction with operand types Gv and Ev. The first operand (Gv) indicates a general register that is a word or doubleword. The second operand (Ev) indicates that a ModR/M byte follows that specifies whether the operand is a word or doubleword general-purpose register or a memory address. The ModR/M byte for this instruction is 05H, which indicates that a 32-bit displacement follows (00000000H). The reg/opcode portion of the ModR/M byte (bits 3 through 5) is 000 indicating the EAX register. Thus, it can be determined that the instruction for this opcode is ADD EAX, mem_op and the offset of mem_op is 00000000H.  Some 1-byte opcodes point to "group" numbers. These group numbers indicate that the instruction uses the reg/opcode bits in the ModR/M byte as an opcode extension.

 

 

 

We mentioned that the processor handles Interrupts after finishing the current instruction. If it finds a signal on its interrupt pin, it will look up the address of the interrupt handler in the interrupt table and pass that routine control.  After returning from the interrupt handler routine it will resume program execution at the instruction after the interrupted instruction.  Table 105 shows some interrupt assignments in the Intel 386, 486 SX/DX processors, and the Pentium processor.

 

                        __________________________________________________

                        Vector number   Description

                        __________________________________________________

                        0                                  Divide Error (Division by zero)

                        1                                  Debug Interrupt (Single step)

                        2                                  NMI Interrupt

                        3                                  Breakpoint

                        4                                  Interrupt on overflow

                        5                                  BOUND range exceeded

                        6                                  Invalid Opcode

                        7                                  Device not available (1)

                        8                                  Double fault

                        9                                  Not used in DX models and Pentium (2)

                        10                     Invalid TSS

                        11                     Segment not present

                        12                     Stack exception

                        13                     General protection fault

                        14                     Page fault

                        15                     Reserved

                        16                     Floating point exception (3)

                        17                     Alignment check (4)

                        18 - 31              Reserved on 3/486

                        32 - 255            Maskable user-defined interrupts

                        __________________________________________________

 

Table 105 Interrupt Assignments in the Intel 386, 486 SX/DX Processors, and the Pentium Processor

 

 

  1. Exception 7 is used to signal that a floating-point processor is not present in the SX model. Exception 7 is used for programs and OS that have floating point emulation.  Also the DX chips can be set to trap floating point instructions by setting bit 2 of CR0.
  2. Exception 9 is reserved in the DX models and the Pentium, and is only used in the 3/486 SX models to signal Coprocessor segment overrun. This will cause an Abort type exception on the SX.
  3. In the SX models this exception is called “Coprocessor error”.
  4. Alignment check is only defined in 486 and Pentiums. Reserved on any other Intel processor.
  5. For Pentiums Exception 18 is used to signal what is called a “Machine check exception”.
  6. The other interrupts, (32-255) are user defined. They differ in use from one OS to another.

This list is a brief description of each of the 256 interrupts. Each description begins with "INT nn " where "nn" is a two digit hexadecimal number 00 - FF for automatic processing.

 

INT 00 - CPU-generated - DIVIDE ERROR

INT 01 - CPU-generated - SINGLE STEP; (80386+) - DEBUGGING EXCEPTIONS

INT 02 - external hardware - NON-MASKABLE INTERRUPT

INT 03 - CPU-generated - BREAKPOINT

INT 04 - CPU-generated - INTO DETECTED OVERFLOW

INT 05 - PRINT SCREEN; CPU-generated (80186+) - BOUND RANGE EXCEEDED

INT 06 - CPU-generated (80286+) - INVALID OPCODE

INT 07 - CPU-generated (80286+) - PROCESSOR EXTENSION NOT AVAILABLE

INT 08 - IRQ0 - SYSTEM TIMER; CPU-generated (80286+)

INT 09 - IRQ1 - KEYBOARD DATA READY; CPU-generated (80286,80386)

INT 0A - IRQ2 - LPT2/EGA,VGA/IRQ9; CPU-generated (80286+)

INT 0B - IRQ3 - SERIAL COMMUNICATIONS (COM2); CPU-generated (80286+)

INT 0C - IRQ4 - SERIAL COMMUNICATIONS (COM1); CPU-generated (80286+)

INT 0D - IRQ5 - FIXED DISK/LPT2/reserved; CPU-generated (80286+)

INT 0E - IRQ6 - DISKETTE CONTROLLER; CPU-generated (80386+)

INT 0F - IRQ7 - PARALLEL PRINTER

INT 10 - VIDEO; CPU-generated (80286+)

INT 11 - BIOS - GET EQUIPMENT LIST; CPU-generated (80486+)

INT 12 - BIOS - GET MEMORY SIZE

INT 13 - DISK

INT 14 - SERIAL

INT 15 - CASSETTE

INT 16 - KEYBOARD

INT 17 - PRINTER

INT 18 - DISKLESS BOOT HOOK (START CASSETTE BASIC)

INT 19 - SYSTEM - BOOTSTRAP LOADER

INT 1A - TIME

INT 1B - KEYBOARD - CONTROL-BREAK HANDLER

INT 1C - TIME - SYSTEM TIMER TICK

INT 1D - SYSTEM DATA - VIDEO PARAMETER TABLES

INT 1E - SYSTEM DATA - DISKETTE PARAMETERS

INT 1F - SYSTEM DATA - 8x8 GRAPHICS FONT

INT 20 - DOS 1+ - TERMINATE PROGRAM

INT 21 - DOS 1+ - Function Calls

INT 22 - DOS 1+ - PROGRAM TERMINATION ADDRESS

INT 23 - DOS 1+ - CONTROL-C/CONTROL-BREAK HANDLER

INT 24 - DOS 1+ - CRITICAL ERROR HANDLER

INT 25 - DOS 1+ - ABSOLUTE DISK READ

INT 26 - DOS 1+ - ABSOLUTE DISK WRITE

INT 27 - DOS 1+ - TERMINATE AND STAY RESIDENT

INT 28 - DOS 2+ - DOS IDLE INTERRUPT

INT 29 - DOS 2+ - FAST CONSOLE OUTPUT

INT 2A - NETBIOS

INT 2B - DOS 2+ - RESERVED

INT 2C - DOS 2+ - RESERVED

INT 2D - DOS 2+ - RESERVED

INT 2E - DOS 2+ - PASS COMMAND TO COMMAND INTERPRETER FOR EXECUTION

INT 2F - Multiplex

INT 30 - (NOT A VECTOR!) - DOS 1+ - FAR JMP instruction

INT 31 - overwritten by CP/M jump instruction in INT 30

INT 32 - (no special use)

INT 33 - MS MOUSE

INT 34 - FLOATING POINT EMULATION - OPCODE D8h

INT 35 - FLOATING POINT EMULATION - OPCODE D9h

INT 36 - FLOATING POINT EMULATION - OPCODE DAh

INT 37 - FLOATING POINT EMULATION - OPCODE DBh

INT 38 - FLOATING POINT EMULATION - OPCODE DCh

INT 39 - FLOATING POINT EMULATION - OPCODE DDh

INT 3A - FLOATING POINT EMULATION - OPCODE DEh

INT 3B - FLOATING POINT EMULATION - OPCODE DFh

INT 3C - FLOATING POINT EMULATION - SEGMENT OVERRIDE

INT 3D - FLOATING POINT EMULATION - STANDALONE FWAIT

INT 3E - FLOATING POINT EMULATION - Borland "SHORTCUT" CALL

INT 3F - Overlay manager interrupt (Microsoft/Borland)

INT 40 - DISKETTE - RELOCATED ROM BIOS DISKETTE HANDLER

INT 41 - SYSTEM DATA - HARD DISK 0 PARAMETER TABLE; CPU - MS Windows

INT 42 - VIDEO - RELOCATED DEFAULT INT 10 VIDEO SERVICES (EGA,VGA)

INT 43 - VIDEO DATA - CHARACTER TABLE (EGA,MCGA,VGA)

INT 44 - VIDEO DATA - CHARACTER FONT (PCjr); Novell NetWare

INT 45 - Z100/Acorn

INT 46 - SYSTEM DATA - HARD DISK 1 DRIVE PARAMETER TABLE

INT 47 - Z100/Acorn/Western Digital/SQL Base

INT 48 - KEYBOARD (PCjr) - Z100/Watstar/Acorn/Western Digital/Compaq

INT 49 - SYSTEM DATA (PCjr) - Z100/TI/Watstar/Acorn/MAGic

INT 4A - SYSTEM - USER ALARM HANDLER

INT 4B - IBM SCSI interface; Virtual DMA Specification (VDS)

INT 4C - Z100/Acorn/TI

INT 4D - Z100

INT 4E - TI/Z100

INT 4F - Common Access Method SCSI

INT 50 - IRQ0 relocated by software

INT 51 - IRQ1 relocated by software

INT 52 - IRQ2 relocated by software

INT 53 - IRQ3 relocated by software

INT 54 - IRQ4 relocated by software

INT 55 - IRQ5 relocated by software

INT 56 - IRQ6 relocated by software

INT 57 - IRQ7 relocated by software

INT 58 - IRQ8/0 relocated by software

INT 59 - IRQ9/1 relocated by software; GSS Computer Graphics Interface

INT 5A - IRQ10/2 relocated by software

INT 5B - IRQ11/3 relocated by software; Network

INT 5C - IRQ12/4 relocated by software; Network Interface

INT 5D - IRQ13/5 relocated by software

INT 5E - IRQ14/6 relocated by software

INT 5F - IRQ15/7 relocated by software; HP 95LX GRAPHICS PRIMITIVES

INT 60 - reserved for user interrupt; multiple purposes

INT 61 - reserved for user interrupt; multiple purposes

INT 62 - reserved for user interrupt; multiple purposes

INT 63 - reserved for user interrupt; multiple purposes

INT 64 - reserved for user interrupt; multiple purposes

INT 65 - reserved for user interrupt; multiple purposes

INT 66 - reserved for user interrupt; multiple purposes

INT 67 - reserved for user interrupt; LIM EMS; multiple purposes

INT 68 - multiple purposes

INT 69 - multiple purposes

INT 6A - multiple purposes

INT 6B - multiple purposes

INT 6C - CONVERTIBLE; DOS 3.2; DECnet DOS network scheduler

INT 6D - VGA - internal

INT 6E - DECnet DOS - DECnet NETWORK PROCESS API

INT 6F - Novell NetWare; 10NET; MS Windows 3.0

INT 70 - IRQ8 - CMOS REAL-TIME CLOCK

INT 71 - IRQ9 - REDIRECTED TO INT 0A BY BIOS

INT 72 - IRQ10 - RESERVED

INT 73 - IRQ11 - RESERVED

INT 74 - IRQ12 - POINTING DEVICE (PS)

INT 75 - IRQ13 - MATH COPROCESSOR EXCEPTION (AT and up)

INT 76 - IRQ14 - HARD DISK CONTROLLER (AT and later)

INT 77 - IRQ15 - RESERVED (AT,PS); POWER CONSERVATION (Compaq)

INT 78 - DOS extenders; multiple purposes

INT 79 - multiple purposes

INT 7A - Novell NetWare; IBM 3270; multiple purposes

INT 7B - multiple purposes

INT 7C - multiple purposes

INT 7D - multiple purposes

INT 7E - RESERVED FOR DIP, Ltd. ROM LIBRARY; multiple purposes

INT 7F - multiple purposes

INT 80 - reserved for BASIC; multiple purposes

INT 81 - reserved for BASIC

INT 82 - reserved for BASIC

INT 83 - reserved for BASIC

INT 84 - reserved for BASIC

INT 85 - reserved for BASIC

INT 86 - IBM ROM BASIC - used while in interpreter; multiple purposes

INT 87 - IBM ROM BASIC - used while in interpreter

INT 88 - IBM ROM BASIC - used while in interpreter; multiple purposes

INT 89 - IBM ROM BASIC - used while in interpreter

INT 8A - IBM ROM BASIC - used while in interpreter

INT 8B - IBM ROM BASIC - used while in interpreter

INT 8C - IBM ROM BASIC - used while in interpreter

INT 8D - IBM ROM BASIC - used while in interpreter

INT 8E - IBM ROM BASIC - used while in interpreter

INT 8F - IBM ROM BASIC - used while in interpreter

INT 90 - IBM ROM BASIC - used while in interpreter

INT 91 - IBM ROM BASIC - used while in interpreter

INT 92 - IBM ROM BASIC - used while in interpreter; multiple purposes

INT 93 - IBM ROM BASIC - used while in interpreter

INT 94 - IBM ROM BASIC - used while in interpreter; multiple purposes

INT 95 - IBM ROM BASIC - used while in interpreter

INT 96 - IBM ROM BASIC - used while in interpreter

INT 97 - IBM ROM BASIC - used while in interpreter

INT 98 - IBM ROM BASIC - used while in interpreter

INT 99 - IBM ROM BASIC - used while in interpreter

INT 9A - IBM ROM BASIC - used while in interpreter

INT 9B - IBM ROM BASIC - used while in interpreter

INT 9C - IBM ROM BASIC - used while in interpreter

INT 9D - IBM ROM BASIC - used while in interpreter

INT 9E - IBM ROM BASIC - used while in interpreter

INT 9F - IBM ROM BASIC - used while in interpreter

INT A0 - IBM ROM BASIC - used while in interpreter

INT A1 - IBM ROM BASIC - used while in interpreter

INT A2 - IBM ROM BASIC - used while in interpreter

INT A3 - IBM ROM BASIC - used while in interpreter

INT A4 - IBM ROM BASIC - used while in interpreter

INT A5 - IBM ROM BASIC - used while in interpreter

INT A6 - IBM ROM BASIC - used while in interpreter

INT A7 - IBM ROM BASIC - used while in interpreter

INT A8 - IBM ROM BASIC - used while in interpreter

INT A9 - IBM ROM BASIC - used while in interpreter

INT AA - IBM ROM BASIC - used while in interpreter

INT AB - IBM ROM BASIC - used while in interpreter

INT AC - IBM ROM BASIC - used while in interpreter

INT AD - IBM ROM BASIC - used while in interpreter

INT AE - IBM ROM BASIC - used while in interpreter

INT AF - IBM ROM BASIC - used while in interpreter

INT B0 - IBM ROM BASIC - used while in interpreter

INT B1 - IBM ROM BASIC - used while in interpreter

INT B2 - IBM ROM BASIC - used while in interpreter

INT B3 - IBM ROM BASIC - used while in interpreter

INT B4 - IBM ROM BASIC - used while in interpreter

INT B5 - IBM ROM BASIC - used while in interpreter

INT B6 - IBM ROM BASIC - used while in interpreter

INT B7 - IBM ROM BASIC - used while in interpreter

INT B8 - IBM ROM BASIC - used while in interpreter

INT B9 - IBM ROM BASIC - used while in interpreter

INT BA - IBM ROM BASIC - used while in interpreter

INT BB - IBM ROM BASIC - used while in interpreter

INT BC - IBM ROM BASIC - used while in interpreter

INT BD - IBM ROM BASIC - used while in interpreter

INT BE - IBM ROM BASIC - used while in interpreter

INT BF - IBM ROM BASIC - used while in interpreter

INT C0 - IBM ROM BASIC - used while in interpreter

INT C1 - IBM ROM BASIC - used while in interpreter

INT C2 - IBM ROM BASIC - used while in interpreter

INT C3 - IBM ROM BASIC - used while in interpreter

INT C4 - IBM ROM BASIC - used while in interpreter

INT C5 - IBM ROM BASIC - used while in interpreter

INT C6 - IBM ROM BASIC - used while in interpreter

INT C7 - IBM ROM BASIC - used while in interpreter

INT C8 - IBM ROM BASIC - used while in interpreter

INT C9 - IBM ROM BASIC - used while in interpreter

INT CA - IBM ROM BASIC - used while in interpreter

INT CB - IBM ROM BASIC - used while in interpreter

INT CC - IBM ROM BASIC - used while in interpreter

INT CD - IBM ROM BASIC - used while in interpreter

INT CE - IBM ROM BASIC - used while in interpreter

INT CF - IBM ROM BASIC - used while in interpreter

INT D0 - IBM ROM BASIC - used while in interpreter

INT D1 - IBM ROM BASIC - used while in interpreter

INT D2 - IBM ROM BASIC - used while in interpreter

INT D3 - IBM ROM BASIC - used while in interpreter

INT D4 - IBM ROM BASIC - used while in interpreter

INT D5 - IBM ROM BASIC - used while in interpreter

INT D6 - IBM ROM BASIC - used while in interpreter

INT D7 - IBM ROM BASIC - used while in interpreter

INT D8 - IBM ROM BASIC - used while in interpreter

INT D9 - IBM ROM BASIC - used while in interpreter

INT DA - IBM ROM BASIC - used while in interpreter

INT DB - IBM ROM BASIC - used while in interpreter

INT DC - IBM ROM BASIC - used while in interpreter

INT DD - IBM ROM BASIC - used while in interpreter

INT DE - IBM ROM BASIC - used while in interpreter

INT DF - IBM ROM BASIC - used while in interpreter

INT E0 - IBM ROM BASIC - used while in interpreter; multiple purposes

INT E1 - IBM ROM BASIC - used while in interpreter

INT E2 - IBM ROM BASIC - used while in interpreter

INT E3 - IBM ROM BASIC - used while in interpreter

INT E4 - IBM ROM BASIC - used while in interpreter

INT E5 - IBM ROM BASIC - used while in interpreter

INT E6 - IBM ROM BASIC - used while in interpreter

INT E7 - IBM ROM BASIC - used while in interpreter

INT E8 - IBM ROM BASIC - used while in interpreter

INT E9 - IBM ROM BASIC - used while in interpreter

INT EA - IBM ROM BASIC - used while in interpreter

INT EB - IBM ROM BASIC - used while in interpreter

INT EC - IBM ROM BASIC - used while in interpreter

INT ED - IBM ROM BASIC - used while in interpreter

INT EE - IBM ROM BASIC - used while in interpreter

INT EF - BASIC - ORIGINAL INT 09 VECTOR

INT F0 - BASICA.COM, GWBASIC, compiled BASIC - ORIGINAL INT 08 VECTOR

INT F1 - reserved for user interrupt

INT F2 - reserved for user interrupt

INT F3 - reserved for user interrupt

INT F4 - reserved for user interrupt

INT F5 - reserved for user interrupt

INT F6 - reserved for user interrupt

INT F7 - reserved for user interrupt

INT F8 - reserved for user interrupt

INT F9 - reserved for user interrupt

INT FA - reserved for user interrupt

INT FB - reserved for user interrupt

INT FC - reserved for user interrupt

INT FD - reserved for user interrupt

INT FE - AT/XT286/PS50+ - destroyed by return from protected mode

INT FF - AT/XT286/PS50+ - destroyed by return from protected mode

_______________________________________________________________________

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupts under Intel Architecture

 

 

            We talked a little about the Intel processor architecture, but now we will see it in more detail.  The Intel architecture processor supports procedure calls in the following two different ways: CALL and RET instructions. ENTER and LEAVE instructions, in conjunction with the CALL and RET instructions. Both of these procedure call mechanisms use the procedure stack to save the state of the calling procedure, pass parameters to the called procedure, and store local variables for the currently executing procedure. The processor’s facilities for handling interrupts and exceptions are similar to those used by the CALL and RET instructions.

 

 

The processor responds to interrupts and exceptions in essentially the same way. When an interrupt or exception is signaled, the processor halts execution of the current program or task and switches to a handler procedure that has been written specifically to handle the interrupt or exception condition. The processor accesses the handler procedure through an entry in the interrupt descriptor table (IDT). When the handler has completed handling the interrupt or exception, program control is returned to the interrupted program or task. The operating system, executive, and/or device drivers normally handle interrupts and exceptions independently from application programs or tasks. Application programs can, however, access the interrupt and exception handlers incorporated in an operating system or executive through assembly-language calls.

 

 

The IA-32 Architecture defines 17 predefined interrupts and exceptions and 224 user defined interrupts, which are associated with entries in the IDT. Each interrupt and exception in the IDT is identified with a number, called a vector. Table 106 lists the interrupts and exceptions with entries in the IDT and their respective vector numbers. Vectors 0 through 8, 10 through 14, and 16 through 19 are the predefined interrupts and exceptions, and vectors 32 through 255 are the user-defined interrupts, called maskable interrupts.  Note that the processor defines several additional interrupts that do not point to entries in the IDT; the most notable of these interrupts is the SMI interrupt.   When the processor detects an interrupt or exception, it does one of the following things:

            a.  Executes an implicit call to a handler procedure.

b.      Executes an implicit call to a handler task.

 

Vector No.

Mnemonic

Description

Source

0

#DE

Divide Error

DIV and IDIV instructions.

1

#DB

Debug

Any code or data reference.

 

 

NMI Interrupt

Non-maskable external interrupt.

3

#BP

Breakpoint

INT 3 instruction.

4

#OF

Overflow

INTO instruction.

5

#BR

BOUND Range Exceeded

BOUND instruction.

6

#UD

Invalid Opcode (UnDefined Opcode)

UD2 instruction or reserved opcode.

7

#NM

Device Not Available (No Math Coprocessor)

Floating-point or WAIT/FWAIT instruction.

8

#DF

Double Fault

Any instruction that can generate an exception, an NMI, or an INTR.

9

#MF

CoProcessor Segment Overrun (reserved)

Floating-point instruction.

10

#TS

Invalid TSS

Task switch or TSS access.

11

#NP

Segment Not Present

Loading segment registers or accessing system segments.

12

#SS

Stack Segment Fault

Stack operations and SS register loads.

13

#GP

General Protection

Any memory reference and other protection checks.

14

#PF

Page Fault

Any memory reference.

15

 

(Intel reserved. Do not use.)

 

16

#MF

Floating-Point Error (Math Fault)

Floating-point or WAIT/FWAIT instruction.

17

#AC

Alignment Check

Any data reference in memory.

18

#MC

Machine Check

Error codes (if any) and source are model dependent.

19

#XF

SIMD Floating-Point Exception

SIMD Floating-Point Instruction

20-31

 

(Intel reserved. Do not use.)

 

32-255

 

Maskable Interrupts

External interrupt from INTR pin or INT n instruction.

 

Table 106 Exceptions and Interrupts

A call to an interrupt or exception handler procedure is similar to a procedure call to another protection level. Here, the interrupt vector references one of two kinds of gates: an interrupt gate or a trap gate. Interrupt and trap gates are similar to call gates in that they provide the following information:

 

a)      Access rights information.  

b)      The segment selector for the code segment that contains the handler procedure. 

c)      An offset into the code segment to the first instruction of the handler procedure.

 

The difference between an interrupt gate and a trap gate is as follows. If an interrupt or exception handler is called through an interrupt gate, the processor clears the interrupt enable (IF) flag in the EFLAGS register to prevent subsequent interrupts from interfering with the execution of the handler. When a handler is called through a trap gate, the state of the IF flag is not changed.

 

If the code segment for the handler procedure has the same privilege level as the currently executing program or task, the handler procedure uses the current stack; if the handler executes at a more privileged level, the processor switches to the stack for the handler’s privilege level. If no stack switch occurs, the processor does the following when calling an interrupt or exception handler:

 

  1. Pushes the current contents of the EFLAGS, CS, and EIP registers (in that order) on the stack.
  2.  Pushes an error code (if appropriate) on the stack.
  3.  Loads the segment selector for the new code segment and the new instruction pointer (from the interrupt gate or trap gate) into the CS and EIP registers, respectively.
  4.  If the call is through an interrupt gate, clears the IF flag in the EFLAGS register.
  5. Begins execution of the handler procedure at the new privilege level.

If a stack switch does occur, the processor does the following:

  1. Temporarily saves (internally) the current contents of the SS, ESP, EFLAGS, CS, and EIP registers.
  2. Loads the segment selector and stack pointer for the new stack (that is, the stack for the privilege level being called) from the TSS into the SS and ESP registers and switches to the new stack.
  3. Pushes the temporarily saved SS, ESP, EFLAGS, CS, and EIP values for the interrupted procedure’s stack onto the new stack.
  4. Pushes an error code on the new stack (if appropriate).
  5. Loads the segment selector for the new code segment and the new instruction pointer (from the interrupt gate or trap gate) into the CS and EIP registers, respectively.
  6. If the call is through an interrupt gate, clears the IF-flag in the EFLAGS register.
  7. Begins execution of the handler procedure at the new privilege level.

A return from an interrupt or exception handler is initiated with the IRET instruction. The IRET instruction is similar to the far RET instruction, except that it also restores the contents of the EFLAGS register for the interrupted procedure:

When executing a return from an interrupt or exception handler from the same privilege level as the interrupted procedure, the processor performs these actions:

  1. Restores the CS and EIP registers to their values prior to the interrupt or exception.
  2. Restores the EFLAGS register.
  3. Increments the stack pointer appropriately
  4. Resumes execution of the interrupted procedure.

When executing a return from an interrupt or exception handler from a different privilege level than the interrupted procedure, the processor performs these actions:

  1. Performs a privilege check.
  2. Restores the CS and EIP registers to their values prior to the interrupt or exception.
  3. Restores the EFLAGS register.
  4. Restores the SS and ESP registers to their values prior to the interrupt or exception, resulting in a stack switch back to the stack of the interrupted procedure.
  5. Resumes execution of the interrupted procedure.

 

Interrupt and exception handler routines can also be executed in a separate task. Here, an interrupt or exception causes a task switch to a handler task. The handler task is given its own address space and (optionally) can execute at a higher protection level than application programs or tasks.  The switch to the handler task is accomplished with an implicit task call that references a task gate descriptor. The task gate provides access to the address space for the handler task. As part of the task switch, the processor saves complete state information for the interrupted program or task. Upon returning from the handler task, the state of the interrupted program or task is restored and execution continues.

 

The INT n, INTO, INT 3, and BOUND instructions allow a program or task to explicitly call an interrupt or exception handler. The INT n instruction uses an interrupt vector as an argument, which allows a program to call any interrupt handler.  The INTO instruction explicitly calls the overflow exception (#OF) handler if the overflow flag (OF) in the EFLAGS register is set.  The OF flag indicates overflow on arithmetic instructions, but it does not automatically raise an overflow exception. An overflow exception can only be raised explicitly in either of the following ways:

 

a)      Execute the INTO instruction.

b)      Test the OF flag and execute the INT n instruction with an argument of 4 (the vector number of the overflow exception) if the flag is set.

 

Both the methods of dealing with overflow conditions allow a program to test for overflow at specific places in the instruction stream.  The INT 3 instruction explicitly calls the breakpoint exception (#BP) handler.  The BOUND instruction explicitly calls the BOUND-range exceeded exception (#BR) handler if an operand is found to be not within predefined boundaries in memory.   Like the overflow exception, the BOUND-range exceeded exception can only be raised explicitly with the BOUND instruction or the INT n instruction with an argument of 5 (the vector number of the bounds-check exception). The processor does not implicitly perform bounds checks and raise the BOUND-range exceeded exception. When operating on individual or packed floating-point values, the IA-32 architecture supports a set of six floating-point exceptions. These exceptions can be generated during operations performed by the x87 FPU instructions or by the SSE and SSE2 instructions. When an x87 FPU instruction generates one or more of these exceptions, it in turn generates an floating-point error exception (#MF); when an SSE and SSE2 instruction generates a floating-point exception, it in turn generates a SIMD floating-point exception (#XF).

 

            As we can see, interrupt and exception handling varies from Operating Systems and hardware architecture. The 8259A PIC is a good example of how these Interrupts are handled by the hardware.  Of course new interrupt handlers have been developed such as the External Interrupt Controller Using Intel 80310 I/O Processor Chipset.  We saw how the Intel architecture processor handles interrupts and exceptions.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

References:

            All the information in this research paper was obtained from the Internet. These are the web pages visited as of May 13, 2002:

 

<http://www.psych.mcgill.ca/perpg/stds/rk/Aurora/memoma_c.htm>

<http://developer.intel.com/design/intarch/techinfo/pentium/fpuhandl.htm>

<http://support.intel.com/support/controllers/peripheral/7277.htm>

<http://www.altera.com/products/ip/ampp/cast/m-cas-8259a.html>

<http://www.intel.com/design/Pentium4/manuals/24547006.pdf>

<http://www.internals.com/articles/protmode/interrupts.htm>

<http://www.delorie.com/djgpp/doc/ug/interrupts/inthandlers1.html>

< http://www.delorie.com/djgpp/doc/ug/interrupts/inthandlers2.html>

<http://www.tldp.org/LDP/tlk/tlk-toc.html>

< http://cs-alb-pc3.massey.ac.nz/notes/59304/l11.html>

< http://www.cs.adfa.oz.au/~spike/CSA2/Lectures00/lecture.interrupts.htm>

< http://www.pcguide.com/ref/mbsys/res/irq/func.htm>